ipxe-github

Michael Brown 5b3ebf8b24 [riscv] Support T-Head CPUs using non-standard Memory Attribute Extension Xuantie/T-Head processors such as the C910 (as used in the Sipeed Lichee Pi 4A) use the high bits of the PTE in a very non-standard way that is incompatible with the RISC-V specification. As per the "Memory Attribute Extension (XTheadMae)", bits 62 and 61 represent cacheability and "bufferability" (write-back cacheability) respectively. If we do not enable these bits, then the processor gets incredibly confused at the point that paging is enabled. The symptom is that cache lines will occasionally fail to fill, and so reads from any address may return unrelated data from a previously read cache line for a different address. Work around these hardware flaws by detecting T-Head CPUs (via the "get machine vendor ID" SBI call), then reading the vendor-specific SXSTATUS register to determine whether or not the vendor-specific Memory Attribute Extension has been enabled by the M-mode firmware. If it has, then set bits 61 and 62 in each page table entry that is used to access normal memory. Signed-off-by: Michael Brown <mcb30@ipxe.org>		2 days ago
.github/workflows	[ci] Update action versions to silence GitHub warnings	1 year ago
contrib	[crypto] Switch to using python-asn1crypto instead of python-asn1	2 months ago
src	[riscv] Support T-Head CPUs using non-standard Memory Attribute Extension	2 days ago
COPYING	[legal] Update GPLv2 licence text	10 years ago
COPYING.GPLv2	[legal] Update GPLv2 licence text	10 years ago
COPYING.UBDL	[legal] Add support for the Unmodified Binary Distribution Licence	10 years ago
README	[build] Rename gPXE to iPXE	15 years ago

README

iPXE README File

Quick start guide:

   cd src
   make

For any more detailed instructions, see http://ipxe.org