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[misc] arch/cpu refactoring
[misc] arch/cpu refactoring
* Move the cpu.c/cpu.h in more logical places and remove these sources files. * Add detection for LoongArch64 EFI bootloaders. * Pass the detected CPU arch when invoking Fido. * Also fix some Bled Coverity warnings.pull/2636/head

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16 changed files with 121 additions and 260 deletions
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2.vs/rufus.vcxproj
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6.vs/rufus.vcxproj.filters
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2src/Makefile.am
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19src/Makefile.in
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9src/bled/header_verbose_list.c
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1src/bled/libbb.h
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123src/cpu.c
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79src/cpu.h
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87src/hash.c
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4src/iso.c
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5src/missing.h
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11src/net.c
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3src/parser.c
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8src/rufus.c
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12src/rufus.h
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10src/rufus.rc
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/* |
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* Rufus: The Reliable USB Formatting Utility |
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* CPU features detection |
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* Copyright © 2022 Pete Batard <pete@akeo.ie> |
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* Copyright © 2022 Jeffrey Walton <noloader@gmail.com> |
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* |
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* This program is free software: you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License as published by |
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* the Free Software Foundation, either version 3 of the License, or |
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* (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program. If not, see <http://www.gnu.org/licenses/>. |
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*/ |
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|
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#include "cpu.h" |
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#if (defined(CPU_X86_SHA1_ACCELERATION) || defined(CPU_X86_SHA256_ACCELERATION)) |
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#if defined(RUFUS_MSC_VERSION) |
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#include <intrin.h> |
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#elif (defined(RUFUS_GCC_VERSION) || defined(RUFUS_CLANG_VERSION)) |
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#include <x86Intrin.h> |
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#elif defined(RUFUS_INTEL_VERSION) |
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#include <immintrin.h> |
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#endif |
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#endif |
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BOOL cpu_has_sha1_accel = FALSE; |
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BOOL cpu_has_sha256_accel = FALSE; |
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|
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/* |
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* Three elements must be in place to make a meaningful call to the |
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* DetectSHA###Acceleration() calls. First, the compiler must support |
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* the underlying intrinsics. Second, the platform must provide a |
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* cpuid() function. And third, the cpu must actually support the SHA-1 |
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* and SHA-256 instructions. |
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* |
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* If any of the conditions are not met, then DetectSHA###Acceleration() |
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* returns FALSE. |
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*/ |
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|
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/* |
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* Detect if the processor supports SHA-1 acceleration. We only check for |
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* the three ISAs we need - SSSE3, SSE4.1 and SHA. We don't check for OS |
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* support or XSAVE because that's been enabled since Windows 2000. |
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*/ |
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BOOL DetectSHA1Acceleration(void) |
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{ |
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#if defined(CPU_X86_SHA1_ACCELERATION) |
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#if defined(_MSC_VER) |
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uint32_t regs0[4] = {0,0,0,0}, regs1[4] = {0,0,0,0}, regs7[4] = {0,0,0,0}; |
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const uint32_t SSSE3_BIT = 1u << 9; /* Function 1, Bit 9 of ECX */ |
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const uint32_t SSE41_BIT = 1u << 19; /* Function 1, Bit 19 of ECX */ |
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const uint32_t SHA_BIT = 1u << 29; /* Function 7, Bit 29 of EBX */ |
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__cpuid(regs0, 0); |
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const uint32_t highest = regs0[0]; /*EAX*/ |
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if (highest >= 0x01) { |
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__cpuidex(regs1, 1, 0); |
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} |
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if (highest >= 0x07) { |
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__cpuidex(regs7, 7, 0); |
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} |
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|
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return (regs1[2] /*ECX*/ & SSSE3_BIT) && (regs1[2] /*ECX*/ & SSE41_BIT) && (regs7[1] /*EBX*/ & SHA_BIT) ? TRUE : FALSE; |
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#elif defined(__GNUC__) || defined(__clang__) |
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/* __builtin_cpu_supports available in GCC 4.8.1 and above */ |
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return __builtin_cpu_supports("ssse3") && __builtin_cpu_supports("sse4.1") && __builtin_cpu_supports("sha") ? TRUE : FALSE; |
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#elif defined(__INTEL_COMPILER) |
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/* https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_may_i_use_cpu_feature */ |
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return _may_i_use_cpu_feature(_FEATURE_SSSE3|_FEATURE_SSE4_1|_FEATURE_SHA) ? TRUE : FALSE; |
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#else |
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return FALSE; |
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#endif |
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#else |
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return FALSE; |
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#endif |
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} |
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|
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/* |
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* Detect if the processor supports SHA-256 acceleration. We only check for |
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* the three ISAs we need - SSSE3, SSE4.1 and SHA. We don't check for OS |
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* support or XSAVE because that's been enabled since Windows 2000. |
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*/ |
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BOOL DetectSHA256Acceleration(void) |
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{ |
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#if defined(CPU_X86_SHA256_ACCELERATION) |
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#if defined(_MSC_VER) |
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uint32_t regs0[4] = {0,0,0,0}, regs1[4] = {0,0,0,0}, regs7[4] = {0,0,0,0}; |
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const uint32_t SSSE3_BIT = 1u << 9; /* Function 1, Bit 9 of ECX */ |
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const uint32_t SSE41_BIT = 1u << 19; /* Function 1, Bit 19 of ECX */ |
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const uint32_t SHA_BIT = 1u << 29; /* Function 7, Bit 29 of EBX */ |
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__cpuid(regs0, 0); |
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const uint32_t highest = regs0[0]; /*EAX*/ |
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if (highest >= 0x01) { |
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__cpuidex(regs1, 1, 0); |
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} |
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if (highest >= 0x07) { |
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__cpuidex(regs7, 7, 0); |
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} |
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return (regs1[2] /*ECX*/ & SSSE3_BIT) && (regs1[2] /*ECX*/ & SSE41_BIT) && (regs7[1] /*EBX*/ & SHA_BIT) ? TRUE : FALSE; |
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#elif defined(__GNUC__) || defined(__clang__) |
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/* __builtin_cpu_supports available in GCC 4.8.1 and above */ |
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return __builtin_cpu_supports("ssse3") && __builtin_cpu_supports("sse4.1") && __builtin_cpu_supports("sha") ? TRUE : FALSE; |
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#elif defined(__INTEL_COMPILER) |
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/* https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_may_i_use_cpu_feature */ |
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return _may_i_use_cpu_feature(_FEATURE_SSSE3|_FEATURE_SSE4_1|_FEATURE_SHA) ? TRUE : FALSE; |
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#else |
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return FALSE; |
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#endif |
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#else |
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return FALSE; |
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#endif |
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} |
@ -1,79 +0,0 @@ |
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/* |
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* Rufus: The Reliable USB Formatting Utility |
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* CPU features detection |
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* Copyright © 2022 Pete Batard <pete@akeo.ie> |
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* Copyright © 2022 Jeffrey Walton <noloader@gmail.com> |
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* |
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* This program is free software: you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License as published by |
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* the Free Software Foundation, either version 3 of the License, or |
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* (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program. If not, see <http://www.gnu.org/licenses/>. |
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*/ |
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|
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/* |
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* Primarily added to support SHA instructions on x86 machines. |
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* SHA acceleration is becoming as ubiquitous as AES acceleration. |
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* SHA support was introduced in Intel Goldmont architecture, like |
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* Celeron J3455 and Pentium J4205. The instructions are now present |
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* in AMD Ryzen 3 (Zen architecture) and above, and Intel Core |
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* 10th-gen processors (Ice Lake), 11th-gen processors (Rocket Lake) |
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* and above. |
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* |
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* Typical benchmarks for x86 SHA acceleration is about a 6x to 10x |
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* speedup over a C/C++ implementation. The rough measurements are |
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* 1.0 to 1.8 cpb for SHA-1, and 1.5 to 2.5 cpb for SHA-256. On a |
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* Celeron J3455, that's 1.1 GB/s for SHA-1 and 800 MB/s for SHA-256. |
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* On a 10th-gen Core i5, that's about 1.65 GB/s for SHA-1 and about |
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* 1.3 GB/s for SHA-256. |
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*/ |
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#include "rufus.h" |
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#pragma once |
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#ifdef _MSC_VER |
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#define RUFUS_MSC_VERSION (_MSC_VER) |
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#if (RUFUS_MSC_VERSION < 1900) |
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#error "Your compiler is too old to build this application" |
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#endif |
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#endif |
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#if defined(__GNUC__) |
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#define RUFUS_GCC_VERSION (__GNUC__ * 10000 + __GNUC_MINOR__ * 100 + __GNUC_PATCHLEVEL__) |
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#if (RUFUS_GCC_VERSION < 40900) |
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#error "Your compiler is too old to build this application" |
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#endif |
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#endif |
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#ifdef __INTEL_COMPILER |
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#define RUFUS_INTEL_VERSION (__INTEL_COMPILER) |
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#if (RUFUS_INTEL_VERSION < 1600) |
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#error "Your compiler is too old to build this application" |
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#endif |
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#endif |
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#if defined(__clang__) |
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#define RUFUS_CLANG_VERSION (__clang_major__ * 10000 + __clang_minor__ * 100 + __clang_patchlevel__) |
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#if (RUFUS_CLANG_VERSION < 30400) |
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#error "Your compiler is too old to build this application" |
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#endif |
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#endif |
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#if (defined(_M_IX86) || defined(_M_X64) || defined(__i386__) || defined(__i386) || \ |
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defined(_X86_) || defined(__I86__) || defined(__x86_64__)) |
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#define CPU_X86_SHA1_ACCELERATION 1 |
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#define CPU_X86_SHA256_ACCELERATION 1 |
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#endif |
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extern BOOL cpu_has_sha1_accel, cpu_has_sha256_accel; |
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|
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extern BOOL DetectSHA1Acceleration(void); |
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extern BOOL DetectSHA256Acceleration(void); |
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